The present invention relates to a method for analysis prior to design of a transmission line from a large scale integrated circuit (LSI) chip through an intermediate substrate to a printed circuit board. The present invention also relates to an analysis apparatus for performing such a method. Further, the present invention relates to a computer-readable storage medium having a program recorded thereon for executing such a method.
As LSI technology has been developed in recent years, computer aided engineering (CAE) has been used to design LSI chips to obtain a high operation speed. An electromagnetic field simulator has been put to practical use so as to solve Maxwell equations of three-dimensional models. For example, according to a conventional method of determining an equivalent circuit, which is disclosed in FIG. 4 of Japanese laid-open patent publication No. 8-51134, a circuit model is designed as follows. An inductance L and a ground capacitance C are used as a circuit model in a state in which a lead pin of a package having an LSI chip mounted thereon is mounted on a board (printed circuit board). Then, fitting is conducted so that the circuit model accords with S parameters calculated by an electromagnetic field simulator. In this manner, design models from 1 GHz to 6 GHz can be obtained.
Meanwhile, according to finer integration of LSIs, flip chip (FC) ball grid array (BGA) packages are used as a kind of high-speed LSI packages having a large number of pins for input and output signals.
FIG. 1 is an exterior perspective view showing an example of an FC-BGA. As shown in FIG. 1, the FC-BGA has an LSI chip 800, a printed circuit board 810, and an interposer 820 serving as an intermediate substrate for relaying signal lines from the LSI chip 800 to the printed circuit board 810. The packaged LSI chip 800 and interposer 820 is mounted on the printed circuit board 810.
FIG. 2 is a perspective view showing a main portion of the FC-BGA shown in FIG. 1. As shown in FIG. 2, the FC-BGA includes an LSI chip 800, a printed circuit board 810, and an interposer 820 serving as an intermediate substrate for relaying signal lines from the LSI chip 800 to the printed circuit board 810. The LSI chip 800 and the interposer 820 are electrically connected to each other via FC bumps (not shown). The interposer 820 and the printed circuit board 810 are electrically connected to each other via solder balls 822. The LSI chip 800 has an electrode pad electrically connected to the solder balls 822 via interposer transmission lines 824 and vias 830 in the interposer 820. The solder balls 822 are electrically connected to a printed circuit board transmission line 840 via a pad (not shown) provided on a surface of the printed circuit board 810.
In this FC-BGA, wiring pitches in the LSI chip 800 and wiring pitches in the printed circuit board 810 differ from each other by about three orders of magnitude. Accordingly, the interposer 820 is important in packaging design of FC-BGA because the interposer 820 absorbs scale differences between the pitches in the electrode pad of the LSI chip 800 and the pitches in the pad of the printed circuit board 810.
FIG. 3A is a schematic cross-sectional view of the interposer 820 shown in FIG. 1. FIG. 3B shows an equivalent circuit of the interposer 820 for analysis. As shown in FIG. 3A, the interposer includes an FC pad 850 for connection with the electrode pad of the LSI chip 800, a first via 831, an interposer transmission line 826, a second via 832, a third via 833, a fourth via 834, a relay line 827, a fifth via 835, and a BGA land 852 for connection with the solder ball. The first via 831, the interposer transmission line 826, the second via 832, the third via 833, the fourth via 834, the relay line 827, and the fifth via 835 are connected between the FC pad 850 and the BGA land 852 in the order named. As shown in FIG. 3A, the interposer has a multilayer structure including a plurality of conductive layers. In the following description, a portion connecting between different conductive layers in a direction perpendicular to a substrate surface of the interposer is referred to as an interlayer connecting section.
As shown in FIG. 3B, the FC pad 850 is replaced with a port 1, and the BGA land 852 is replaced with a port 2. Then, circuit constants for analysis are applied to the respective components from the first via 831 to the fifth via 835 so that each via is represented as a circuit model. Further, S parameters are applied to the interposer transmission line 826 and the relay line 827 so that each of the interposer transmission line 826 and the relay line 827 is represented as an S parameter model. Thus, the circuit models and the S parameter models are used to perform electromagnetic field analysis. This example employs mixed models of the circuit models and the S parameter models. In the following description, circuit models and S parameter models are referred to as analysis models.
The conventional method of determining an equivalent circuit, as disclosed by Japanese laid-open patent publication No. 8-51134, has the following drawbacks.
First, a design model of CAE cannot represent electric characteristics in a high-frequency range (GHz band). Accordingly, high speed cannot be maintained at currents ranging from a direct current to a high-frequency current at the time of design. Particularly, digital LSIs are required to represent characteristics in a high-frequency range because interconnections in the digital LSIs are used as wide-band transmission lines to achieve a high speed of processing. In a case of design of such high-speed multipin LSIs, a three-dimensional electromagnetic field analysis as shown in FIG. 2 should be performed to attach great importance to high-frequency characteristics of models to be generated.
However, the aforementioned method requires a large scale of a model. When the LSI has many terminals, computer resources cannot design the entire model but can design only part of the model. The method disclosed by Japanese laid-open patent publication No. 8-51134 generates a partial characteristic model including a lead pin and a board. Accordingly, this method can only be employed in an electromagnetic field analysis for the illustrated number of pins or several pins.
As described above, in the conventional method in which priority is given to high-frequency characteristics, characteristic analysis can be performed only for several pins. Thus, the entire multipin LSI cannot be modeled by the conventional method. Accordingly, only specific pins are represented by a model for operation analysis. Specifically, since a model representing high-frequency characteristics has a large scale, it cannot be applied to a multipin model. Thus, a model representing high-frequency characteristics cannot be utilized for packaging design (design for operational guarantee from an LSI chip through an interposer to a printed circuit board). Additionally, a designer should determine which parts to be extracted from the whole circuit to generate a model for specific pins. Thus, generated models are different in precision of test for high-frequency characteristics depending on the skill of designers.
When the entire transmission line from the LSI chip through the interposer to the printed circuit board is represented by the analysis models as shown in FIG. 3, it is possible to perform an analysis of a multipin model with certain computer resources. However, since the analysis model shown in FIG. 3 cannot represent high-frequency characteristics at a GHz band, it is difficult to guarantee the performance. Specifically, the conventional method cannot generate a model that can represent both of high-frequency characteristics and the entire characteristics from the LSI chip through the interposer to the printed circuit board and that can be employed for multipin design.
Second, high-frequency characteristics of high-speed multipin LSIs are tested based on data measured in a state in which an object (packaged LSI) is mounted on a board. Specifically, a product specification is determined, and the packaged LSI is mounted and measured after high-frequency LSI design, chip fabrication, packaging assembly, and inspection. Then, design, fabrication, and inspection are repeated. Thereafter, product fabrication is started. Accordingly, a large amount of time and cost is needed to accumulate data obtained from measurement and to reflect the data on design models.